In mixed mode integrated circuits with large analog blocks, such as high-speed serial interfaces, there is a need to analyze the health of the analog blocks of the integrated circuit while in operation. The joint test action group (JTAG) standard can be used to test a failure along the connectivity path between chips. However, this is limited to the interfacing circuits of the integrated circuit, specifically the input/output circuitry and routing, and does not provide access to voltages inside an analog block. Another drawback of the JTAG standard is the use of a scan chain which can only read out the voltages in a fixed sequence. The scan chain mechanism does not generally help test for timing or other dynamic operational errors that may occur. Additionally, it is desirable to keep the system running in place and being able to debug the system without having to shut it down. Faulty components in a system are often tested one at a time, which requires bringing down the system and debugging each component separately.
It is in this context that embodiments of the invention arise.